Designing clock distribution for a WCDMA transceiver system

Clock distribution devices create and distribute multiple copies of a master clock to a variety of integrated circuits (ICs). These devices have single-ended or differential clock inputs and provide multiple outputs (single ended or differential), which are typically divided and delayed versions of the input clock. Low-phase-noise Crystal Oscillators (XOs) are commonly used to drive clock distribution devices. The sinusoidal input signal to a clock distribution device is converted to a number of square wave outputs. Statistical variations of the input reference clock and clock signal processing causes clock jitter, so a Phase Locked Loop (PLL) is often included to improve the jitter of the output clock.